Technical Field
The present disclosure relates to three dimensional integrated circuits (3D IC), and more specifically, to a 3D package having a latency compensation network using timing slack sensors.
Related Art
Three dimensional (3D) packages are manufactured by stacking silicon wafers and/or dies and interconnecting them vertically using through silicon vias (TSVs). For example, a 3D package may include a CPU tier and a memory tier. Using this approach, 3D packages behave as a single device that achieves performance improvements with reduced power and a smaller footprint than conventional two dimensional devices. Because of the proximity of the tiers, 3D packaging can, e.g., reduce off-chip main memory access latencies by 45-60%.
One of the associated challenges of 3D packaging is the potential introduction of delay faults that can occur between the different tiers. Defects, such as manufacturing variability, contamination, resistive open/shorts, etc., can result in an abnormally slow propagation of a signal from one tier to another. This type of defect can potentially violate the timing specification during at-speed operations and result in functional errors. Unfortunately, many such delay faults are not detectable by static tests, e.g., using stuck-at fault models.